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| MB81EDS516545 (Continued) * Optional commands and features -Multi Bank Active (MACT) -Multi Bank Precharge (MPRE) -Background Refresh (BREF) -Additional RDQS Toggle (ART) 2 DS05-11463-1E MB81EDS516545 1. Clock Inputs (CK and CK) CK and CK are differential clock inputs. All address and control input signals are sampled on the rising edge of CK. And the rising edge of CK and the rising edge of CK increment device internal address counter and drive even and odd data input/out respectively. tCK CK tCH CK tCL tCK tDC tDC tCH tCL 2. Clock Enable (CKE) CKE is a high active clock enable signal. When CKE = Low is latched at the rising edge of CK, the next CK rising edge will be invalid. CKE controls power down mode and self refresh mode. CK CK CKE tIS tIS CK (Internal) 3. Chip Select (CS) CS enables all commands inputs, RAS, CAS, and WE, and address inputs. CS = High disable command input but internal operation such as burst cycle will not be suspended. 4. Command Inputs (RAS, CAS and WE) The combination of RAS, CAS, and WE input in conjunction with CS at a rising edge of the CK define the command for device operation. Refer to the "COMMAND TRUTH TABLE". 5. Bank Address Inputs (BA0, BA1) BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. 4 DS05-11463-1E MB81EDS516545 6. Address Inputs (A0 to A12) Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix. Total 21 address input signals are required to decode such a matrix. Row Address (RA) is input from A0 to A12 and Column Address (CA) is input from A0 to A7. Row addresses are latched with ACTIVE (ACT or MACT) commands, and Column addresses and Auto Precharge (AP) bit are latched with Read (READ or READA) or Write command (WRIT or WRITA). * Command and address inputs setup and hold time CK tIS Command (CS, RAS, CAS, WE) Address tIH tIPW 7. Input Data Mask (DM0 to DM7) DM is an input mask signal for write data. Input data is masked when DM is sampled High on the both edges of WDQS along with input data. DM0, DM1, DM2, DM3, DM4, DM5, DM6 and DM7 correspond to DQ[7:0], DQ[15:8], DQ[23:16], DQ[31:24], DQ[39:32], DQ[47:40], DQ[55:48] and DQ[63:56] respectively. Refer to the "DQ/RDQS/WDQS/DM Correspondence Table". 8. Data Bus Input / Output (DQ0 to DQ63) DQ is data bus input / output signal. 9. Read Data Strobe (RDQS0 to RDQS3) RDQS is output signal transmitted by memory during read operation. RDQS is edge aligned with output data. RDQS0, RDQS1, RDQS2 and RDQS3 correspond to DQ[15:0], DQ[31:16], DQ[47:32] and DQ[63:48] respectively. Refer to the "DQ/RDQS/WDQS/DM Correspondence Table". After stable power supply, RDQS outputs Low. DS05-11463-1E 5 MB81EDS516545 BLOCK DIAGRAM CK CK CKE CLOCK BUFFER To each block VDDQ VDD VSS VSSQ A[12:0] ADDRESS BUFFER BURST COUNTROLLER Y CONTROLLER Bank3 Bank2 Bank1 Bank0 X CONTROLLER MEMORY CELL ARRAY (2 M bit x 64) BA[1:0] SA ADDRESS COUNTROLLER CS RAS CAS WE COMMAND DECODER MODE REGISTER MEMORY CORE CONTROLLER READ AMP WRITE AMP DM[7:0] RDQS[3:0] I/O BUFFER WDQS[3:0] BUS CONTROLLER DQ[63:0] DS05-11463-1E 7 MB81EDS516545 SIMPLIFIED STATE DIAGRAM SELF REFRESH SELF DEEP POWER DOWN DPD MRS PDX MODE REGISTER SET ACT POWER DOWN SELFX REF IDLE PD AUTO REFRESH BANK ACTIVE BST WRIT DPDX WRIT WRITE WRITA WRITA PRE READA PD PDX BST READ READ ACTIVE POWER DOWN READ READA WRITE WITH AUTO PRECHARGE PRE PRE READ WITH AUTO PRECHARGE POWER ON PRE PRECHARGE Automatic Sequence POWER APPLIED Manual Input Note: "SIMPLIFIED STATE DIAGRAM" is based on the single bank operation. State transition of multi bank operation are not described in all detail. 8 DS05-11463-1E MB81EDS516545 3. Burst Length (BL) Burst Length (BL) is the number of word to be read or write as the result of a single READ or WRITE command. It can be set on 2, 4, 8, 16 words boundary through Mode Register. The burst type is sequential that is incremental decoding scheme within a boundary address to be determined by burst length. Device internal address counter assigns +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address ( = 0). Starting Column Address Burst Burst Address Sequence Length (Hexadecimal) A3 A2 A1 A0 2 X X X 4 X X X X X X 8 X X X X X 0 0 0 0 0 0 0 16 0 1 1 1 1 1 1 1 1 X X X X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E DS05-11463-1E 11 MB81EDS516545 4. CAS Latency (CL) CAS Latency (CL) is the delay between READ command being registered and first read data becoming available during read operation. First read data will be valid after (CL-1) x tCK + tAC from the CK rising edge where Read command being latched. 5. Driver Strength (DS) Driver Strength (DS) is to adjust the driver strength of data output. 6. Pre Driver Strength (PDS) Pre Driver Strength (PDS) is to adjust the transition time of the data output without changing the output driver impedance. 7. Additional RDQS Toggle (ART) Additional RDQS Toggle (ART) is to set RDQS toggle count after the last pair of data output. Total RDQS toggle count is BL/2 + ART. RDQS Timing with Additional RDQS Toggle (ART) function @BL=4 CK CK RDQS ART = 0 RDQS ART = 1 1 additional RDQS toggle RDQS ART = 2 2 additional RDQS toggles RDQS ART = 3 3 additional RDQS toggles DQ (Output) Q0 Q1 Q2 Q3 12 DS05-11463-1E MB81EDS516545 3) Single Bank Operation Current State CS RAS CAS WE IDLE H L L L L L L L L BANK ACTIVE H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACT/MACT PRE/PALL/ MPRE REF/BREF MRS DESL NOP BST READ/READA WRIT/WRITA ACT/MACT PRE/PALL/ MPRE REF/BREF MRS NOP Illegal *1 NOP Function Bank Active NOP *2 Auto Refresh or Background Refresh *3 Mode Register Set *3, *4 Start Read; Determine AP Start Write; Determine AP Illegal *1 Precharge; Determine Precharge Type Illegal (Continued) DS05-11463-1E 15 MB81EDS516545 Current State READ CS H L L L L L L L L RAS CAS WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACT/MACT PRE/PALL/ MPRE REF/BREF MRS DESL NOP BST READ/READA WRIT/WRITA ACT/MACT PRE/PALL/ MPRE REF/BREF MRS Illegal *1 NOP Function Burst Terminate BANK ACTIVE Interrupt burst read by new burst read; Determine AP Illegal Illegal *1 Terminate burst read by precharge IDLE Illegal NOP Burst terminate BANK ACTIVE Interrupt burst write by new burst read; Determine AP *5 Interrupt burst write by new burst write; Determine AP WRITE H L L L L L L L L Illegal (Continued) 16 DS05-11463-1E MB81EDS516545 Current State Write Recovering CS H L L L L L L L L RAS CAS WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACT/MACT PRE/PALL/ MPRE REF/BREF MRS DESL NOP BST READ/READA WRIT/WRITA ACT/MACT PRE/PALL/ MPRE REF/BREF MRS NOP *2 Illegal Illegal *1 Illegal *1 Illegal NOP Function Start Write; Determine AP Illegal NOP Illegal Precharging H L L L L L L L L (Continued) 18 DS05-11463-1E MB81EDS516545 (Continued) Current State Bank Activating CS H L L L L L L L L RAS CAS WE X H H H H L L L L X H H H X H H L L H H L L X H H L X H L H L H L H L X H L X Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X X Command DESL NOP BST READ/READA WRIT/WRITA ACT/MACT PRE/PALL/ MPRE REF/SELF/BREF MRS DESL NOP BST READ/READA/ WRIT/WRITA ACT/MACT/PRE/ PALL/MPRE/ REF/SELF/ BREF/MRS Illegal Illegal NOP Illegal *2 NOP Function Refreshing/ Mode Register Setting H L L L L L X X X RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge Note: Assuming CKE = H during the previous clock cycle and the current clock cycle. After illegal commands are asserted, following command and stored data should not be guaranteed. *1: Illegal to bank in the specified state. Command entry may be legal depending on the state of bank selected by BA. *2: NOP to bank in precharging or in idle state. Bank in active state may be precharged depending on BA. *3: Illegal if any bank is not idle. *4: MRS command should be issued on condition that all DQ are in High-Z. *5: Requires appropriate DM masking. DS05-11463-1E 19 MB81EDS516545 BANK OPERATION COMMAND TABLE Minimum clock latency or delay time for single bank operation 2nd Command (same bank) READA BREFX *8 WRITA MACT MPRE tMRD tRAS *3 READ MRS ACT READ READA WRIT WRITA READ BST WRIT BST PRE PALL REF SELFX MACT MPRE BREF BREFX tMRD tMRD tMRD tMRD tMRD tMRD tMRD tMRD tMRD tRCD *4 tRCD tRCD *6 *5 tRCD *6 tRAS tRAS *1, *2 BL/2 + tRP BL/2 +1 + tDAL 1 1 BL/2 +CL BL/2 +CL 1 *3 *3 1 BL/2 + tRP *3 1 BL/2 + tRP *3 *1 *1, *2 BL/2 + tRP BL/2 +1 + tDAL 1 BL/2 + tRP *3 BL/2 + tRP *1, *2 *6 *6 BL/2 + tRP BL/2 + tRP *1 BL/2 + tRP *1, *2 BL/2 + tRP BL/2 +1 + tDAL 2 + tWTR 2 + tWTR 1 1 1 BL/2 +1 + tDAL BL/2 +1 + tWR BL/2 +1 + tDAL *3 BL/2 +1 + tWR BL/2 +1 + tDAL *3 BL/2 +1 + tWR BL/2 +1 + tDAL 1 1 + tWR 1 BL/2 +1 + tDAL BL/2 +1 + tDAL BL/2 +1 + tDAL 1 1 + tWTR 1 1 + tWTR CL CL 1 1 *3 1 *3 1st Command 1 1 1 + tWR tRP 1 1 + tWR 1 *1, *2 tRP tRP *1 *1, *2 tRP tRP tRP *2 tRP tRP tRP 1 1 tRP *2 tRP tRP 1 tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC *7 *7 *7 *7 tRCD tRCD tRCD tRCD tRAS 1 + tRAS 1 + tRAS *1, *2 tRP RC x tREFC tRP tRP 1 1 *1 *1, *2 tRP RC x tREFC tRP RC x tREFC tRP 1 RC x tREFC RC x tREFC RC x tREFC RC x tREFC RC x tREFC RC x tREFC BREF tRP tRP tRP tREFC PALL SELF WRIT MRS ACT PRE BST REF tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC " - " : illegal *1: Assume all banks are in IDLE state. *2: Assume output is in High-Z state. *3: Assume tRAS (Min.) is satisfied. *4: ACT to READA interval must be longer than tRAS - BL/2. *5: ACT to WRITA interval must be longer than tRAS - (1 + BL/2 + tWR). *6: Assume appropriate DM masking. *7: 1st read or write access must be allowed for appropriate bank specified in the ACT and MACT commands of "COMMAND TRUTH TABLE". *8: BREFX command can be issued only when Background Refresh is in progress. 20 DS05-11463-1E MB81EDS516545 Minimum clock latency or delay time for multi bank operation 2nd Command (other bank) READA BREFX *7 WRITA MPRE tMRD 1 MACT READ MRS ACT READ READA WRIT WRITA READ BST WRIT BST PRE PALL REF SELFX MACT MPRE BREF BREFX " - " : illegal tMRD tMRD tMRD tMRD tMRD tMRD tMRD tMRD tMRD tRRD 1 1 1 *5 1 *5 1 1 tRAS tRRD tRRD BREF 1 1 1 1 1 1 tRP tREFC tREFC tRRD 1 RC x tREFC tREFC PALL WRIT SELF MRS ACT PRE BST REF tRRD *1, *2 *1, *3 1 1 1 BL/2 +CL *5 BL/2 +CL *5 1 1 *4 1 *4 *1 *1 *1, *3 1 1 *7 1 BL/2 + tRP *1 *1, *3 1 BL/2 *5 BL/2 *5 BL/2 +CL 1 BL/2 +CL 1 BL/2 + tRP 1 BL/2 + tRP *4 BL/2 + tRP *1 BL/2 + tRP *1 *1, *3 1 1 *7 1 *1, *3 1 2 + tWTR *5 2 + tWTR *5 1 BL/2 +1 + tDAL 1 BL/2 +1 + tWR *4 *1, *3 1 1 *7 1 BL/2 +1 + tDAL *1, *3 1 BL/2 +1 + tWTR 1 BL/2 +1 + tWTR 1 1 + tWTR 1 BL/2 BL/2 1 BL/2 +1 + tDAL *4 BL/2 +1 + tDAL BL/2 +1 + tDAL *1, *3 1 1 *7 1 CL CL 1 1 1 *4 1st Command *1, *3 *1, *3 1 1 + tWTR *1, *3 1 1 *7 1 1 1 1 1 + tWR 1 *1, *2 tRP 1 1 1 1 1 1 *1 *1, *2 *1, *3 tRP tRP 1 1 *7 1 *1 tRP tRP tRP 1 1 tRP tRP tRP 1 tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tREFC tRRD *6 *6 *6 *6 1 1 1 1 1 1 1+ tRAS tRRD 1 *7 tRRD *1, *2 *1, *3 tRP RC x tREFC 1 1 1 1 1 1 1 1 *1 *1, *2 *1, *3 tRP RC x tREFC tRP RC x tREFC 1 1 *7 1 tRRD 1 1 1 1 1 1 RC x tREFC tRRD 1 *7 tREFC tREFC tRRD 1 1 1 1 1 1 tREFC tREFC tREFC tRRD 1 *1: Assume other bank is in IDLE state. *2: Assume output is in High-Z state. *3: Assume tRRD is satisfied. *4: Assume tRAS is satisfied. *5: Assume appropriate DM masking. *6: 1st read or write access must be allowed for appropriate bank specified in the ACT and MACT commands of "COMMAND TRUTH TABLE". *7: BREFX command can be issued only when Background Refresh is in progress. DS05-11463-1E 21 MB81EDS516545 COMMAND DESCRIPTION 1. DESELECT (DESL) When CS is High at the CK rising edge, all input signals are neglected. Internal operation such as burst cycle is held. 2. NO OPERATION (NOP) NOP disables address and data input and internal operation such as burst cycle is held. 3. BANK ACTIVE (ACT) ACT activates the bank selected by BA and latch the row address through A0 to A12. 4. READ (READ) READ initiates burst read operation to an activated row address. Address inputs of A[7:0] determine starting column address and A10 determines whether Auto Precharge is used or not. Initially RDQS output Low level then start toggling together with data output with respect to CL and BL. The read data output is edge-aligned with first rising edge of RDQS and successive read data output are edge-aligned to the successive edge of RDQS. The CK drives the rising edge of RDQS and Even data, and the CK drives the falling edge of RDQS and Odd data. 22 DS05-11463-1E MB81EDS516545 CK CK CAS Latency Command READ NOP tAC (Min.) RDQS tDQSCK tDQSCK tLZ DQ tQH Qeven tQH Qodd Qeven Qodd tDQSQ tAC tDQSQ tAC tAC(Max.) tDQSCK tDQSCK RDQS tLZ DQ tQH Qeven tDQSQ tAC tAC tDQSQ tQH Qodd 5. READ with Auto Precharge (READA) READA commands can be issued by READ command with AP (A10) = H. Auto precharge is a feature which precharge the activated bank after the completion of burst read operation. The tRAS is defined from between ACTIVE (ACT) command to the internal precharge which starts after BL/2 from READA command. READ with Auto precharge operation should not be interrupted by subsequent READ, READA, WRITE, WRITEA commands. Next ACTIVE (ACT) command can be issued after BL/2 + tRP after READA command. DS05-11463-1E 23 MB81EDS516545 6. WRITE (WRIT) WRIT initiates burst write operation to an active row address. Address inputs of A[7:0] determine starting column address and AP(A10) determines whether Auto Precharge is used or not. WDQS input must be provided in order to latch the input data. WDQS must be brought to Low to satisfy the specified time duration of the Write Preamble Setup Time to CK (tWPRES). Input data window must be guaranteed with specified minimum setup and hold time against edge of WDQS input (tDS, tDH). The input data appearing on DQ is written into memory cell array subject to the DM input logic level appearing coincident with the input data. If a given signal on DM is registered Low, the corresponding data will be written into the cell array. And if a given signal on DM is registered High, the corresponding data will be masked and write will not be executed to that byte. After data input with respect to BL is completed, WDQS must be kept low for the specified minimum value of Write Postamble Time (tWPST). CK CK Command WRIT NOP tDQSS (Min.) WDQS tWPRES tDQSS tDQSH tDQSL tWPST tDSS DQ Qeven tDS DM tDS tDH tDS tDH tDS tDH tDH Qodd tDS tDH Mask tDS tDH tDSH Qodd tDS tDH tDSS tDS tDH tDQSS (Max.) WDQS tWPRES tDQSS tDQSH tDQSL tWPST tDSS DQ Qeven tDS DM tDS tDH tDS tDH tDS tDH Qodd tDS tDH tDSH Mask tDS tDH Qodd tDS tDH tDSS tDH tDS tDH 24 DS05-11463-1E MB81EDS516545 7. WRITE with Auto Precharge (WRITA) WRITA commands can be issued by WRIT command with AP (A10) = H. Auto precharge is a feature which precharge the activated bank after the completion of burst write operation. The tRAS is defined from between ACTIVE (ACT) command to the internal precharge which starts after 1+ BL/2 + tWR from WRITA command. WRIT with Auto precharge operation should not be interrupted by subsequent READ, READA, WRIT, WRITA commands. Next ACTIVE (ACT) command can be issued after 1+ BL/2 + tDAL after WRITA command. 8. BURST TERMINATE (BST) BST terminates the burst read or write operation. When a burst read is terminated by BST command, the data output will be in High-Z after CAS latency from the BST command. When a burst write is terminated by BST command, the data input after 1 clock from BST command will be masked. Terminate read by BST @CL=3 CK CL = 3 Command NOP READ BST CL = 3 NOP DQ (output) Q0 Q1 Terminate write by BST CK 1 clock Command NOP WRIT BST NOP Masked by BST DQ (input) D0 D1 D2 D3 DS05-11463-1E 25 MB81EDS516545 9. PRECHARGE SINGLE BANK (PRE) PRECHARGE SINGLE BANK (PRE) command starts precharge operation for a bank selected by BA. A selected bank will be in IDLE state after specified time duration of tRP from PRE command. A10 determines whether one or all banks are precharged. If AP(A10) = L, a bank to be selected by BA is precharged. 10. PRECHARGE ALL BANK (PALL) PRECHARGE ALL BANKS (PALL) command starts precharge operation for all banks. All banks will be in IDLE state after specified time duration of tRP from PALL command. A10 determines whether one or all banks are precharged. If AP(A10) = H, all banks are precharged and BA input is a "don't care". 11. AUTO REFRESH (REF) AUTO REFRESH (REF) command starts internal refresh operation which uses the internal refresh address counter. All banks must be precharged prior to the Auto-refresh command. Data retention capability depends on the Junction Temperature (Tj). Total 8,192 AUTO REFRESH (REF) commands must be asserted within the following refresh period of tREF. Tj Max ( C) + 105 + 125 tREF (ms) 64 16.7 12. SELF-REFRESH ENTRY (SELF) SELF REFRESH ENTRY (SELF) commands can be issued by AUTO REFRESH (REF) command in conjunction with CKE = Low after last read data has been appeared on DQ. During Self Refresh mode, stored data can be retained without external clocking and all inputs except for CKE will be a "don't care". Self refresh mode can be used when Tj is less than + 85C. Auto Refresh must be issued to retain data when Tj is greater than + 85 C. 13. SELF-REFRESH EXIT (SELFX) To exit self-refresh mode, apply minimum tIS after CKE brought High, and then the NO OPERATION command (NOP) or the DESELECT command (DESL) should be asserted within one tREFC period. CKE should be held High within one tREFC period after tIS. Refer to the "(15) Self Refresh Entry and Exit" in "TIMING DIAGRAMS" for the detail. It is recommended to assert an Auto-refresh command just after the tREFC period to avoid the violation of refresh period. 14. MODE REGISTER SET (MRS) MODE REGISTER SET (MRS) commands to program the mode registers. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command. MRS command should only be issued on conditions that all DQs are in High-Z and all banks are in IDLE state. The contents of the mode registers is undefined after the power-up and Deep Power Down Exit. Therefore MRS must be issued to set each content of mode registers after initialization. Refer to the "Power Up Initialization" in " FUNCTIONAL DESCRIPTION". 15. POWER DOWN ENTRY (PD) POWER DOWN ENTRY (PD) commands to drive the device in Power Down mode and maintains low power state as long as CKE is kept Low. During Power Down state, all inputs signals are a "don't care" except for CKE. Power Down mode must be entered on condition that all DQs are in High-Z. 16. POWER DOWN EXIT (PDX) POWER DOWN EXIT (PDX) commands to resume the device from Power Down mode. Any commands can be detected 1 clock after PDX commands. 26 DS05-11463-1E MB81EDS516545 17. DEEP POWER DOWN ENTRY (DPD) DEEP POWER DOWN ENTRY (DPD) commands to drive the device in Deep Power Down mode which is the lowest power consumption but all stored data and the contents of mode registers will be lost. During Deep Power Down state, all inputs signals except for CKE are a "don't care" and all DQs and RDQS will be in High-Z. Deep Power Down mode must be entered on conditions that all DQs are in High-Z and all banks are in IDLE state. 18. DEEP POWER DOWN EXIT (DPDX) DEEP POWER DOWN EXIT (DPDX) commands to resume the device from Deep Power Down mode. Power up initialization procedure must be performed after DPDX commands. Refer to the "Power Up Initialization" in " FUNCTIONAL DESCRIPTION". 19. MULTI BANK ACTIVE (MACT) MULTI BANK ACTIVE (MACT) command activates 2 banks simultaneously selected by BA1. SA must be High to issue MACT command. BA1 determines the target bank group is either Bank 0 & 1 or Bank 2 & 3. And BA0 determines the bank where 1st read or write access can be performed. If MACT command is issued to Bank 0 (or Bank 2) with RA = N, same Row Address of RA = N is activated for Bank 1 (or Bank 3) and 1st read or write access must be allowed for RA=N of Bank 0 (or Bank 2). If MACT command is issued to Bank 1 (or Bank 3) with RA = N, next Row Address of RA = N + 1 is activated for Bank 0 (or Bank 2) and 1st read or write access must be allowed for RA = N of Bank 1 (or Bank 3). If MACT command is issued to Bank 1 (or Bank 3) with RA = FFFh, internal row address counter is wrap around therefore activated Row Address is FFFh for Bank 1 (or Bank 3) and 000h for Bank 0 (or Bank 2). Command Truth Table of ACT and MACT Command Symbol SA BA1 BA0 Row Address A[12:0] L L H L H L H L H RA = N RA = N 1st access Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 0 Bank 1 Bank 2 Bank 3 RA RA = N RA = N RA = N RA = N RA = N RA = N RA = N RA = N 2nd access Bank NA NA NA NA Bank 1 Bank 0 Bank 3 Bank 2 RA = N RA = N + 1 RA = N RA = N + 1 RA BANK ACTIVE ACT L L H H L L H H MULTI BANK ACTIVE MACT H The following memory map example enables to issue effective MACT command for 2-bank interleave access between Bank 0 and Bank 1 or Bank 2 and Bank 3. Memory Map Example for 2-bank interleave access by MACT command Bank RA Bank RA 2 000h 0 000h 3 2 001h 1 0 001h 3 1 2 N-1 0 N-1 3 2 N 1 0 N 3 2 N+1 1 0 N+1 3 1 2 FFFh 0 FFFh 3 2 FFFh 1 0 FFFh 3 1 DS05-11463-1E 27 MB81EDS516545 20. MULTI BANK PRECHARGE (MPRE) MULTI BANK PRECHARGE (MPRE) command starts precharge operation for 2 banks selected by BA1. SA must be High to issue MPRE command. Selected 2 banks will be in IDLE state after specified time duration of tRP from MPRE command. BA1 determines whether the target bank group is Bank 0 & 1 or Bank 2 & 3. If MPRE command is issued to BA1 = L, Bank 0 and Bank 1 will be precharged simultaneously. If MPRE command is issued to BA1 = H, Bank 2 and Bank 3 will be precharged simultaneously. Command Truth Table of PRE, PALL and MPRE Command Symbol CS RAS CAS WE A10 A[9:0], BA1 BA0 (AP) A11, A12 L L H L H X X H L L L H H X L H SA Precharged Bank Bank 0 Bank 1 Bank 2 Bank 3 All Banks PRECHARGE SINGLE BANK PRE L L H L L X PRECHARGE ALL BANK MULTI BANK PRECHARGE PALL MPRE H Bank 0 & 1 Bank 2 & 3 21. BACKGROUND REFRESH ENTRY (BREF) BACKGROUND REFRESH ENTRY (BREF) command starts internal refresh operation for 2 banks selected by BA1. SA must be High to issue BREF command and A10 determines either BACKGROUND REFRESH ENTRY (BREF) or EXIT (BREFX). 2 banks which will be refreshed must be precharged prior to the BREF command. When BREF command is issued, Refresh Count (RC) must be set through A[9:0] inputs as shown in the following table. RC defines how many refresh cycle is executed by one BREF command. RC can be set from 1 to 31 cycles. Refreshed banks will be in REFRESH state for a period specified by RC x tREFC. While any read and write access must not be performed during AUTO REFRESH which initiates all banks refresh, background refresh can allow to read or write access to 2 banks which are not refreshed. BA1 determines the target bank group either Bank 0 & 1 or Bank 2 & 3. If BREF command is issued to BA1 = L, Bank 0 & 1 will be refreshed and Bank 2 & 3 can be accessible. If BREF command is issued to BA1 = H, Bank 2 & 3 will be refreshed and Bank 0 & 1 can be accessible. 8,192 BREF command must be asserted to both bank group of Bank 0 & 1 and Bank 2 & 3 within the refresh period of tREF. When background refresh is in progress for one bank group, BREF command must not be issue to the other bank group. 22. BACKGROUND REFRESH EXIT (BREFX) BACKGROUND REFRESH EXIT (BREFX) command terminates internal refresh operation for 2 banks initiated by BREF command for a period of RC x tREFC. SA must be High to issue BREFX command. 2 banks will be IDLE state after tREFC from BREFX command. BREFX command can be issued when background refresh is in progress. 28 DS05-11463-1E MB81EDS516545 Command Truth Table of BREF and BREFX Command AUTO REFRESH BACKGROUND REFRESH ENTRY Symbol CS RAS CAS WE A10 A[9:0], BA1 BA0 (AP) A11, A12 X L X X X SA L Refreshed Bank All Banks Bank 0 & 1 REF BREF L L L H H X L V (RC) H Bank 2 & 3 Bank 0 & 1 BACKGROUND REFRESH EXIT BREFX X X H X H Bank 2 & 3 DS05-11463-1E 29 MB81EDS516545 Refresh Count (RC) Definition Table Refresh Count (RC) ILLEGAL* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A10 A[5:9], A11, A12 A4 A3 A2 A1 L L H L L H H L L L H H L H H L L L L H L L H H H L L H H L H H A0 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H * : A[12:0] = 000h must not be set for RC. 30 DS05-11463-1E MB81EDS516545 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Relative to VSS Input / Output Voltage Relative to VSS Short Circuit Output Current Power Dissipation Storage Temperature Symbol VDD,VDDQ VIN, VOUT IOUT PD TSTG Rating -0.5 to +2.3 -0.5 to +2.3 50 1.0 -55 to +125 Unit V V mA W C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage*1 DC Input High Voltage*2 AC Input High Voltage*2 DC Input Low Voltage *3 Symbol VDD, VDDQ VSS, VSSQ VIH (DC) VIH (AC) VIL (DC) VIL (AC) Tj Min. 1.7 0 VDDQ x 0.7 VDDQ x 0.8 -0.3 -0.3 -10 Typ. 1.8 0 Max. 1.9 0 VDDQ + 0.3 VDDQ + 0.3 VDDQ x 0.3 VDDQ x 0.2 +125 Unit V V V V V V C AC Input Low Voltage*3 Junction Temperature *1: VDDQ must be less than or equal to VDD. *2: Maximum DC voltage on input or I/O pins is VDDQ + 0.3 V. During voltage transitions, inputs may positive overshoot to VDDQ + 1.0V for periods of up to 3 ns. *3: Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, inputs may negative overshoot to VSSQ - 1.0V for periods of up to 3 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. CAPACITANCE Parameter Input Capacitance, Except for WDQS, DM Input Capacitance for WDQS, DM I/O Capacitance Symbol CIN1 CIN2 CI/O Min. 1 2 2 Typ. (Ta = + 25 C, f = 1 MHz) Max. Unit 2.5 4 4 pF pF pF DS05-11463-1E 31 MB81EDS516545 ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating One Bank Active-Precharge Current Symbol (Under recommended operating conditions unless otherwise noted) Value Condition Unit Min. Max. VDDQ - 0.2 -5 -5 0.2 5 5 65 75 6 mA Tj + 125 C Tj + 105 C Tj + 125 C 9 15 20 mA mA V V A A mA mA IOL = 0.1 mA 0 V VIN VDDQ, All other pins not under test = 0 V 0 V VIN VDDQ, Data out disabled tRC = tRC min, tCK = tCK min, CKE = VIH, Tj + 105 C CS = VIH addresses inputs are SWITCHING; Tj + 125 C data bus inputs are STABLE All banks idle, CKE = VIL, CS = VIH, tCK = tCK min, address and control inputs are SWITCHING; data bus inputs are STABLE All banks idle, CKE = VIH, CS = VIH, tCK = tCK min, address and control inputs are SWITCHING; data bus inputs are STABLE One bank active, BL = 4, tCK = tCK min, Output pin open, Gapless data, address inputs are SWITCHING; 50% data change each burst transfer One bank active, BL = 4, tCK = tCK min, Gapless data, address inputs are SWITCHING; 50% data change each burst transfer tRC = tRFC min, tCK = tCK min, CKE = VIH, address and control inputs are SWITCHING; data bus inputs are STABLE Tj + 105 C VOH(DC) IOH = -0.1 mA VOL(DC) ILI ILO IDD0 IDD2P Precharge Standby Current IDD2N Operating Burst Read Current IDD4R 300 mA Operating Burst Write Current IDD4W 380 mA Auto Refresh Current IDD5 120 mA (Continued) 32 DS05-11463-1E MB81EDS516545 (Continued) Parameter Symbol Condition CKE = VIL, CS = VIL, address and control inputs are STABLE; data bus inputs are STABLE address and control inputs are STABLE; data bus inputs are STABLE Value Min. Max. 6 Unit Self Refresh Current IDD6 mA Deep Power Down Current IDD8 300 A Notes: * All voltages are referenced to VSS. * After power on, initialization following power-up timing is required. DC characteristics are guaranteed after the initialization. * IDD depends on the output termination or load condition, clock cycle rate, signal clocking rate. The specified values are obtained with the output open condition. DS05-11463-1E 33 MB81EDS516545 2. AC Characteristics Parameter (Under recommended operating conditions unless otherwise noted)*1, *2 Value Symbol Unit Min. Max. tAC tDQSCK tCH tCL 4 DQ Output Access Time from CK/CK (tCK = tCK min)*3, *4, *7 RDQS Output Access Time from CK/CK *3, *4 Clock High Level Width *3 Clock Low Level Width * 3 2 2 2 2 0.45 15 7.4 4.6 5 0.4 0.5 0.4 0.5 0.35 0.9 0.9 0.6 0 tDC - 0.5 0.75 0.35 0.35 0.2 0.2 2 0 1 6 6 0.55 ns ns ns ns tCK Delay between CK and CK * tDC CL = 2 CL = 3 CL = 4 Tj + 105 C Tj + 125 C Tj + 105 C Tj + 125 C Tj + 105 C Tj + 125 C tDS tDH tDIPW tIS tIH tIPW tLZ tHZ tDQSQ 3, 4 3 Clock Cycle Time tCK ns DQ and DM Input Setup Time*3 DQ and DM Input Hold Time*3 DQ and DM Input Pulse Width Address and Control Input Setup Time *3 Address and Control Input Hold Time * DQ Low-Z Time from CK/CK *3, *5 DQ High-Z Time from CK/CK *3, *5, *6 RDQS to DQ Skew * 4 6 0.4 1.25 ns ns ns ns tCK ns ns tCK ns ns ns ns tCK tCK tCK tCK tCK tCK ns tCK (Continued) Address and Control Input Pulse Width DQ Output Hold Time from RDQS * * WDQS Input High Level Width WDQS Input Low Level Width tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRES tWPST WRIT Command to 1st WDQS Latching Transition WDQS Falling Edge to CK Setup Time WDQS Falling Edge Hold Time from CK MRS Command Period Write Preamble Setup Time Write Postamble Time 34 DS05-11463-1E MB81EDS516545 (Continued) Parameter (Under recommended operating conditions unless otherwise noted)*1, *2 Value Symbol Unit Min. Max. tRAS tRC tREFC tRCD tRP tRRD tWR CL = 2 Data Input to ACT, REF Command Period Internal Write to READ Command Delay Average Refresh Period *9 Average Periodic Refresh Interval Transition Time*10 Tj + 105C Tj + 125C Tj + 105C Tj + 125C CL = 3 CL = 4 tWTR tREFI tREF tT tDAL 37 59.2 100 20 18 9.2 12 1 CLK + tRP 2 CLK + tRP 3 CLK + tRP 9.2 7.8 2.0 64 16.7 1 ns s ms ns ns 8000 ns ns ns ns ns ns ns ACT to PRE, MPRE, PALL Command Period *7 ACT, MACT to ACT, MACT Command Period (Same Bank) *7 REF to ACT, REF Command Period ACT to READ or WRIT Command Period Precharge Period *7 ACT, MACT to ACT, MACT Command Period (Other Bank)*8 Write Recovery Time * 1: AC characteristics are measured after the Power up initialization procedure. * 2: VDD x 0.5 is the reference level for 1.8 V I/O for measuring timing of input/output signals. * 3: If input signal transition time (tT) is longer than 1 ns; [(tT/2) - 0.5] ns should be added to tAC (Max), tDQSCK (Max) and tHZ (max) spec values, [(tT/2) - 0.5] ns should be subtracted from tLZ (Min) and tQH (Min) spec values, and (tT - 1.0) ns should be added to tCH (Min), tCL (Min), tIS (Min), tIH (Min), tDS (Min) and tDH (Min) spec values. * 4: The data valid window is defined as tQH - tDQSQ. The data valid window depends on tDC which is defined between rising edge of CK and rising edge of CK. The data valid window is guaranteed when tDC is satisfied. * 5: tAC, tDQSCK, tLZ and tHZ, are measured under output load circuit shown in " 3. Measurement Condition of AC Characteristics" in " ELECRTRICAL CHARACTERISTICS" and Driver Strength (DS) = Normal, Pre Driver Strength (PDS) = Fast are assumed. * 6: Specified where output buffer is no longer driven. * 7: The sum of actual clock count of tRAS and tRP must be equal or greater than specified minimum tRC. * 8: tRRD is applied to ACT (MACT) to BREF, ACT (MACT) to BREFX, BREF to ACT (MACT) and BREFX to ACT (MACT). Refer to the " BANK OPERATION COMMAND TABLE". * 9: This value is for reference only. * 10: Transition times are measured between VIH (AC) min and VIL (AC) max. DS05-11463-1E 35 MB81EDS516545 3. Measurement Condition of AC Characteristics VDD x 0.5 V 50 DEVICE UNDER TEST 10 pF OUT VDD 0.1 F VSS 36 DS05-11463-1E MB81EDS516545 TIMING DIAGRAMS (1) Read* (Assuming CL = 4, BL = 8) CK CK CKE CS H RAS CAS WE BA BA BA BA BA AP RA RA Address RA CA RA SA DM RDQS WDQS DQ tRCD tRAS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 tRP tRC ACT READ PRE ACT Don't care * : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge DS05-11463-1E 37 MB81EDS516545 (2) Read to Read*1 (Assuming CL = 4, BL = 8) CK CK CKE CS H RAS CAS WE BA 0 1 0 1 1 0 AP RA RA Address RA RA N N M M SA DM RDQS WDQS DQ tRCD tRCD CL = 4 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 CL = 4 CL = 4 CL = 4 ACT Bank 0 ACT Bank 1 READ *2 Bank 0, CA = N READ *2 Bank 1, CA = N READ *2 Bank 1, CA = M READ Bank 0, CA = M Don't care *1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2: Previous burst read can be interrupted by subsequent burst read. 38 DS05-11463-1E MB81EDS516545 (3) Read to Precharge *1(Assuming CL = 4, BL = 8) CK CK CKE CS H RAS CAS WE BA BA BA BA BA BA BA AP RA RA Address RA CA RA CA SA DM RDQS WDQS DQ tRCD CL = 4 Q0 Q1 Q2 Q3 Q0 Q1 tRCD CL = 4*2 CL = 4 tRAS tRC ACT READ PRE*2 tRP tRAS ACT READ PRE Don't care *1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2: Burst read operation can be terminated by PRE command. All DQ pins become High-Z after CL from PRE command. DS05-11463-1E 39 MB81EDS516545 (4) Read with Auto-Precharge *1 (Assuming CL = 4, BL = 8) CK CK CKE CS RAS CAS H WE BA BA BA BA AP Address RA RA RA CA RA SA DM RDQS WDQS DQ tRCD tRAS BL/2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 tRP tRC ACT READA Precharge start*2 ACT*3 Don't care *1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2: Internal precharge operation starts after BL/2 from READA command. tRAS must be satisfied. *3: Next ACT command can be issued after BL/2 + tRP from READA command. tRC must be satisfied. 40 DS05-11463-1E MB81EDS516545 (5) Write *1 (Assuming BL = 8) CK CK CKE CS H RAS CAS WE BA BA BA BA BA AP Address RA RA RA CA RA SA DM RDQS WDQS L DQ tRCD D0 D1 D2 D3 D4 D5 D6 D7 tWR tRAS tRP tRC ACT WRIT PRE*2 ACT Don't care *1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2: Burst write operation should not be terminated by PRE command. PRE can be issued after 1 + BL/2 + tWR from WRIT command. DS05-11463-1E 41 MB81EDS516545 (6) Write to Write *1 (Assuming BL = 8) CK CK CKE CS H RAS CAS WE BA 0 1 0 1 1 0 AP RA RA Address RA RA N N M M SA DM RDQS WDQS L DQ tRCD tRCD D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 ACT Bank 0 ACT Bank 1 WRIT Bank 0, CA = N WRIT*2 Bank 1, CA = N WRIT*2 Bank 1, CA = M WRIT Bank 0, CA = M Don't care *1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2 : Previous burst write can be interrupted by subsequent burst write. 42 DS05-11463-1E MB81EDS516545 (7) Write with Auto-Precharge *1 (Assuming BL = 8) CK CK CKE CS H RAS CAS WE BA BA BA BA AP Address RA RA RA CA RA SA DM RDQS WDQS L DQ tRCD D0 D1 D2 D3 D4 D5 D6 D7 1 + BL/2 tRAS tRC tDAL ACT WRITA Precharge start ACT*2 Don't care *1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2 : Next ACT command can be issued after 1 + BL/2 + tDAL (Min) from WRITA command. tRC must be satisfied. DS05-11463-1E 43 MB81EDS516545 (8) Read to Write *1 (Assuming CL = 4, BL = 8) CK CK H CKE CS RAS CAS WE BA BA BA BA AP RA Address RA CA CA SA DM RDQS WDQS DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 tRCD CL + BL/2*2 ACT READ WRIT Don't care *1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2 : WRIT command can be issued after CL + BL/2 after READ command. 44 DS05-11463-1E MB81EDS516545 (9) Read to Write with BST Command *1 (Assuming CL = 4, BL = 8) CK CK H CKE CS RAS CAS WE BA BA BA BA AP RA Address RA CA CA SA DM RDQS WDQS DQ Q0 Q1 D0 D1 D2 D3 D4 D5 D6 D7 tRCD CL*2 ACT READ BST WRIT Don't care *1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2 : WRIT command can be issued after CL from burst read termination by BST command. DS05-11463-1E 45 MB81EDS516545 (10) Write to Read *1 (Assuming CL = 4, BL = 4) CK CK CKE CS H RAS CAS WE BA BA BA BA AP Address RA RA CA CA SA DM RDQS WDQS DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3 tRCD 1 + BL/2*2 tWTR CL ACT WRIT READ Don't care *1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2 : READ command can be issued after 1 + BL/2 + tWTR from WRIT command. 46 DS05-11463-1E MB81EDS516545 (11) Write to Read with BST Command *1 (Assuming CL = 4, BL = 8) CK CK CKE CS H RAS CAS WE BA BA BA BA AP Address RA RA CA CA SA DM RDQS WDQS DQ D0 D1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Masked by BST*2 tRCD 1 + tWTR CL ACT WRIT BST READ*3 Don't care *1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2 : The data input after 1 clock from BST command will be masked. *3 : READ command can be issued after 1 + tWTR from burst write termination by BST command. DS05-11463-1E 47 MB81EDS516545 (13) DM Control Write *1 (Assuming BL = 8) CK CK CKE CS H RAS CAS WE BA BA BA BA BA AP Address RA RA RA CA RA SA DM RDQS WDQS L DQ tRCD D0 D1 D3 D4 D5 D6 D7 Masked *2 tRAS tRC tWR tRP ACT WRIT PRE ACT Don't care *1 : RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2 : When DM is registered High, the corresponding data will be masked. DS05-11463-1E 49 MB81EDS516545 (15) Self Refresh Entry and Exit *1 CK CK tIS CKE CS RAS CAS WE BA BA AP RA Address RA SA DM RDQS WDQS L DQ tRP tREFC*4,*5 PALL*2 SELF SELFX *3 ACT Don't care *1 : RA = Row Address, BA = Bank Address, AP = Auto Precharge *2 : All banks must be precharged prior to SELF REFRESH ENTRY (SELF) command. *3 : SELF REFRESH EXIT (SELFX) command can be latched at the CK rising edge. *4 : Either NOP or DESL command can be used during tREFC period. *5 : CKE should be held High during tREFC period after SELFX command. DS05-11463-1E 51 MB81EDS516545 (16) Mode Register Set*1 CK CK CKE CS H RAS CAS WE BA Code Code Code BA AP Address Code Code Code RA Code Code Code RA SA DM RDQS WDQS L DQ tRP tREFC tREFC tMRD tMRD tMRD PALL*2 REF REF MRS*2 MRS*2 MRS*2 ACT Don't care *1 : RA = Row Address, BA = Bank Address, AP = Auto Precharge *2 : MODE REGISTER SET (MRS) command must be asserted after all banks have been precharged and all DQ are in High-Z. 52 DS05-11463-1E MB81EDS516545 (19) Deep Power Down Exit *1 CK CK tIS CKE CS RAS CAS WE BA Code Code Code BA AP Code Code Code RA Address Code Code Code RA SA DM RDQS WDQS High-Z DQ 300 s tRP tREFC tREFC tMRD tMRD tMRD DPDX*2 PALL REF REF MRS EMRS EMRS ACT Don't care *1: RA = Row Address, BA = Bank Address, AP = Auto Precharge *2: Power up initialization procedure must be performed after DPDX command. DS05-11463-1E 55 MB81EDS516545 (21) Multi Bank Active to Write to Multi Bank Precharge*1 (Assuming CL = 4, BL = 4) CK CK CS RAS CAS WE BA 0 2 0 1 2 3 0 2 AP Address RA RA RA RA CA CA CA CA SA DM RDQS WDQS DQ D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 tRAS tRCD *2 *2 tRAS tRRD tRCD *3 *3 tWR tWR MACT *2 Bank 0 & 1 MACT *3 Bank 2 & 3 WRIT *2 Bank 0 WRIT *2 Bank 1 WRIT *3 Bank 2 WRIT *3 Bank 3 MPRE Bank 0 & 1 MPRE Bank 2 & 3 Don't care *1: RA = Row Address, BA = Bank Address, CA = Column Address, AP = Auto Precharge *2: If MACT command is issued to Bank 0, 1st WRIT command must be issued to Bank 0 followed by 2nd WRIT command to Bank 1. *3: If MACT command is issued to Bank 2, 1st WRIT command must be issued to Bank 2 followed by 2nd WRIT command to Bank 3. DS05-11463-1E 57 MB81EDS516545 MEMO DS05-11463-1E 59 MB81EDS516545 FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department |
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